Producent |
Numer części |
Arkusz danych Date Size |
Szczegółowy opis |
Rohs Pb Free Lifecycle |
Strona internetowa |
NXP Semiconductors
|
74LVC1G80GW,115
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
unknown
obsolete |
|
Nexperia
|
74LVC1G80GW,115
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
74LVC1G80GW,115
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
NXP Semiconductors
|
74LVC1G80GW,118
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
unknown
obsolete |
|
Nexperia
|
74LVC1G80GW,118
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
74LVC1G80GW,118
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
NXP Semiconductors
|
74LVC1G80GW,125
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
compliant
transferred |
|
Nexperia
|
74LVC1G80GW,125
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
74LVC1G80GW,125
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
NXP Semiconductors
|
74LVC1G80GW,165
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
compliant
obsolete |
|
Nexperia
|
74LVC1G80GW,165
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
74LVC1G80GW,165
|
|
74LVC1G80 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
NXP Semiconductors
|
74LVC1G80GW-Q100,1
|
|
74LVC1G80-Q100 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
compliant
transferred |
|
Nexperia
|
74LVC1G80GW-Q100,1
|
|
74LVC1G80-Q100 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
74LVC1G80GW-Q100,1
|
|
74LVC1G80-Q100 - Single D-type flip-flop; positive-edge trigger TSSOP 5-Pin
|
active |
|
NXP Semiconductors
|
74LVC1G80GW-R
|
|
Single D-type flip-flop; positive-edge trigger - Description: 3.3V PicoGate D-Type Flip-Flop; Positive-Edge Trigger ; Fmax: 450 @ 3.3 V MHz; Logic switching levels: TTL ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Lo
|
compliant no active |
|